Interactive Debugging: Reduce Your Simulation Debug Turn-Around-Time
For most verification engineers, the day starts with understanding and solving yesterday's regression failures. After a nightly regression run, there are usual and customary steps that are taken. Routine tasks include querying failed tests, re-generating the debug database, re-running simulations for more information and also ensuring the correctness of different functional scenarios and testing patterns. Each stage often considerable time commitment and sometimes requires several iterations, lengthening the entire debug process.
To address this challenge, the next-generation Synopsys Verdi® debug platform provides capabilities that assist with avoiding the need to go back and forth among the different steps. However, many users have questions about the process of repeating simulations. This blog reviews considerations verification engineers might have throughout the process and explains how users can take advantage of Verdi features during interactive mode to reduce repeated operations and reduce the time for root cause analysis.
After a nightly regression, I want debugging files ready the next morning.
This is definitley possibly with a feature called "Verdi instant recall". As the regression runs, Verdi instant recall interacts with Synopsys VCS® and provides debugging information to debug any failed test cases. The debugging information specifies which error occurred and where. This information is very helpful for clarifying the error category and where to start debugging without the need to manually rerun the simulations for additional debug data generation.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Blogs
- Is debugging a task, or a continuous process?
- Debugging the iPhone 6
- Verifying and Debugging Storage Protocols: SATA
- Revolutionizing Electronic Circuit Testing and Debugging Using JTAG
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions