Interactive Debugging: Reduce Your Simulation Debug Turn-Around-Time
For most verification engineers, the day starts with understanding and solving yesterday's regression failures. After a nightly regression run, there are usual and customary steps that are taken. Routine tasks include querying failed tests, re-generating the debug database, re-running simulations for more information and also ensuring the correctness of different functional scenarios and testing patterns. Each stage often considerable time commitment and sometimes requires several iterations, lengthening the entire debug process.
To address this challenge, the next-generation Synopsys Verdi® debug platform provides capabilities that assist with avoiding the need to go back and forth among the different steps. However, many users have questions about the process of repeating simulations. This blog reviews considerations verification engineers might have throughout the process and explains how users can take advantage of Verdi features during interactive mode to reduce repeated operations and reduce the time for root cause analysis.
After a nightly regression, I want debugging files ready the next morning.
This is definitley possibly with a feature called "Verdi instant recall". As the regression runs, Verdi instant recall interacts with Synopsys VCS® and provides debugging information to debug any failed test cases. The debugging information specifies which error occurred and where. This information is very helpful for clarifying the error category and where to start debugging without the need to manually rerun the simulations for additional debug data generation.
To read the full article, click here
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Blogs
- Is debugging a task, or a continuous process?
- Debugging the iPhone 6
- Verifying and Debugging Storage Protocols: SATA
- Revolutionizing Electronic Circuit Testing and Debugging Using JTAG
Latest Blogs
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA
- Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments