Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference
September 21, 2017
We are showcasing our HBM2 PHY at the GLOBALFOUNDRIES Technology Conference at the Hyatt Regency Santa Clara (table #6). Designed for systems that require low latency and high bandwidth memory, our HBM2 PHY is built on GLOBALFOUNDRIES advanced 14nm Power Plus (LPP) process technology.
The PHY is fully compliant with the JEDEC HBM2 standard and supports data rates up to 2000 Mbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, as well as support for a stack height of 2, 4 or 8 DRAMs. The PHY is also designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY.
To read the full article, click here
Related Semiconductor IP
- TSMC CLN7FF HBM2E PHY IP
- TSMC CLN5FF HBM PHY IP
- HBM2 Controller IIP
- HBM2E PHY V2 in TSMC (N7, N6, N5)
- HBM2E PHY V2 (Hard 1) in TSMC (N7, N6, N5)
Related Blogs
- Building a robust HBM2 PHY
- Powering the Next Wave of AI Inference with the Rambus GDDR6 PHY at 24 Gb/s
- HBM2E targets AI/ML training
- MIPS and GlobalFoundries: Powering the Next Wave of Physical AI
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space