TSMC CLN7FF HBM2E PHY IP
This datasheet describes the HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide …
Overview
This datasheet describes the HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. The HBM PHY is compliant to the JEDEC HBM2E & HBM2 standard. In 7nm, it supports data rates up to 3200 Mbps per data pin at DFI 1:2 mode. A DFI interface is provided by this HBM PHY IP to connect to HBM memory controller IP. Power information is described at subsection 3.2.1 in detail . Complete signal and power integrity analysis are verified on the GUC design flow to make sure all signal and power requirements are met.
HBM PHY IP includes one hard macro and one RTL module. The hard macro called as IGAHBMX02A is HBM Hard PHY includes command address module, data module, IO pads, PLL and DLL components required for HBM PHY function. The RTL module called as MLB (miscellaneous logic block) is provided to work with HBM Hard PHY. MLB RTL module includes functions such as training logic, JTAG controller interface for PHY DFT registers and BIST(Built-In Self Test) logic. HBM PHY evaluation mode is provided through MLB RTL module without the help of controller to complete the training sequences such as read data EYE training and write data EYE training which are required to guarantee HBM PHY IP functions. MLB training procedure is default enable in initial sequence to set HBM PHY by hardware as described in subsection 3.4.3. This MLB RTL module shall be integrated in SOC by users to work with HBM Hard PHY correctly.
Key features
- High Bandwidth Memory (HBM2E) DRAM PHY
- Supports HBM 3.2Gbps
- Supports DFI 1:2
- Supports only BL4
- Supports AWORD/DWORD bus parity
- Supports programmable parity latency, PL = 0 and 2 , of DQ parity function
- Supports HBM data bus inversion (DBI) and write data mask (DM)
- Complete HBM PHY delivered as a hard macro component (includes I/O, PLL, and DLL)
- Supports HBM PHY internal loopback BIST
- Supports HBM lookback test, includes MISR and LFSR mode
- Supports IEEE 1500 instruction
- Supports HBM lane repairs with redundant pin for row/column/data
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 7nm | N7FF | Silicon Proven |
Specifications
Identity
Files
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Provider
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Frequently asked questions about HBM Interface IP
What is TSMC CLN7FF HBM2E PHY IP?
TSMC CLN7FF HBM2E PHY IP is a HBM IP core from Global UniChip Corp. (GUC) listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this HBM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.