Vendor: Global UniChip Corp. (GUC) Category: HBM

TSMC CLN7FF HBM2E PHY IP

This datasheet describes the HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide …

Controller + PHY + 1 TSMC 7nm N7FF Silicon Proven View all specifications

Overview

This datasheet describes the HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. The HBM PHY is compliant to the JEDEC HBM2E & HBM2 standard. In 7nm, it supports data rates up to 3200 Mbps per data pin at DFI 1:2 mode. A DFI interface is provided by this HBM PHY IP to connect to HBM memory controller IP. Power information is described at subsection 3.2.1 in detail . Complete signal and power integrity analysis are verified on the GUC design flow to make sure all signal and power requirements are met.


HBM PHY IP includes one hard macro and one RTL module. The hard macro called as IGAHBMX02A is HBM Hard PHY includes command address module, data module, IO pads, PLL and DLL components required for HBM PHY function. The RTL module called as MLB (miscellaneous logic block) is provided to work with HBM Hard PHY. MLB RTL module includes functions such as training logic, JTAG controller interface for PHY DFT registers and BIST(Built-In Self Test) logic. HBM PHY evaluation mode is provided through MLB RTL module without the help of controller to complete the training sequences such as read data EYE training and write data EYE training which are required to guarantee HBM PHY IP functions. MLB training procedure is default enable in initial sequence to set HBM PHY by hardware as described in subsection 3.4.3. This MLB RTL module shall be integrated in SOC by users to work with HBM Hard PHY correctly.

Key features

  • High Bandwidth Memory (HBM2E) DRAM PHY
  • Supports HBM 3.2Gbps
  • Supports DFI 1:2
  • Supports only BL4
  • Supports AWORD/DWORD bus parity
  • Supports programmable parity latency, PL = 0 and 2 , of DQ parity function
  • Supports HBM data bus inversion (DBI) and write data mask (DM)
  • Complete HBM PHY delivered as a hard macro component (includes I/O, PLL, and DLL)
  • Supports HBM PHY internal loopback BIST
  • Supports HBM lookback test, includes MISR and LFSR mode
  • Supports IEEE 1500 instruction
  • Supports HBM lane repairs with redundant pin for row/column/data

Silicon Options

Foundry Node Process Maturity
TSMC 7nm N7FF Silicon Proven

Specifications

Identity

Part Number
IGAHBMX02A
Vendor
Global UniChip Corp. (GUC)
Type
Silicon IP
Controller / PHY
Controller + PHY , PHY

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about HBM IP core

Reducing Avoidable Memory Trips In HBM Systems

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Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference

LLM inference is increasingly memory-bound, and HBM cost per GB now dominates system cost. Today’s HBM stacks include short on-die ECC, which tightens binning, raises price, and locks reliability policy inside the device. This paper asks a simple question: can we tolerate a much higher raw HBM bit error rate (BER) and still keep end-to-end correctness and throughput, without changing the HBM PHY or the fixed 32B transaction size?

High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become analogous to the Artificial Intelligence (AI) boom that is everywhere in today’s world. HBM is also increasingly being used in other applications like Data centers, autonomous driving systems, servers, cloud computing just to mention few domains where bandwidth and performance in a key requirement.

Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure

High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, poses a growing barrier to scalable deployment. This work explores a systemlevel approach to cost reduction by eliminating on-die ECC and shifting all fault management to the memory controller.

Frequently asked questions about HBM Interface IP

What is TSMC CLN7FF HBM2E PHY IP?

TSMC CLN7FF HBM2E PHY IP is a HBM IP core from Global UniChip Corp. (GUC) listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this HBM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this HBM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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