Building a robust HBM2 PHY
What is HBM?
HBM is a high-performance memory that features reduced power consumption and a small form factor. More specifically, it combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.
To read the full article, click here
Related Semiconductor IP
- TSMC CLN7FF HBM2E PHY IP
- TSMC CLN5FF HBM PHY IP
- HBM2 Controller IIP
- HBM2E PHY V2 in TSMC (N7, N6, N5)
- HBM2E PHY V2 (Hard 1) in TSMC (N7, N6, N5)
Related Blogs
- Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference
- A Systematic Approach to Robust LVDS Integration in Advanced Node ASICs
- Secure Boot for embedded systems: Building a complete chain of trust
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space