Pipelined Data Masters in D-Series GPUs

By Imagination Technologies Group plc

August 19, 2024

Imagination’s PowerVR GPUs are driven by a firmware processor responsible for high-level scheduling and priority of workloads. It does this in combination with fixed function units: the data masters. To allow concurrent processing of different types of jobs PowerVR GPUs have a data master per job type, including geometry, 3D, compute and 2D (or data movement).

These data masters are responsible for the low-level running of these jobs, including setup work. Previous generations had single-tasking data masters, meaning that the data master would be executing a specific job and changing the job would require work by the firmware processor to set up the next job.

This approach meant that most of the setup work occurred when changing from one render to the next which would often lead to idle time during which the firmware processor was setting up the next job and reprogramming registers. This setup work may have required data access and other complex synchronisation tasks, which due to latency could result in 1000s of cycles of firmware work during which no work was scheduled for the specific data master. This would often lead to idle time or even power-gating of the GPU core and thus lost performance and reduced scaling efficiency.

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