Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms
As silicon manufacturing process nodes keep shrinking and transistors get smaller, System-on-Chip (SoC) are increasingly subject to failures due to changing external conditions such as temperature, EMI, power surges, Hot Plug events, etc.
The transition to PCIe 5.0 and 6.0 with increasing PCIe signaling speeds (32GT/s and 64GT/s) also increases the risk of errors due to constricted timing budgets inside the SoC and electrical issues outside the SoC (e.g. crosstalk, line attenuation, jitter, etc.)
In addition, the ever-growing number of PCIe components and systems designed to different revisions of the Specification increases the risk for interoperability issues.
As a result, chip designers who use PCIe as the main communication interface in their SoCs are looking for ways to bulletproof their designs by implementing advanced Reliability, Availability, and Serviceability (RAS) mechanisms that go above and beyond those included in the PCI Express Base Specification.
We start this article by defining “RAS” in the context of PCIe interfacing and looking at the provisions for RAS mechanisms in the PCIe Specification. We then explore some potential PCIe hazards SoC designers can face and the RAS mechanisms that can be implemented to detect, recover, or prevent these hazards. We conclude with recommendations for choosing a PCIe silicon IP solution that helps mitigate these risks.
To read the full article, click here
Related Semiconductor IP
- PCIe Gen4 RX/TX IP Supporingt PCIe 1.0/2.0/3.0/4.0 up to 16Gbps. CTLE boosts up to 18dB at 8GHz
- PCIe Gen6 Controller
- PCIe Controller IP
- Verification IP for PCIe
- PCIe Gen 7 Verification IP
Related Blogs
- Securing SoC Reliability with Precision Power-On Reset IP for 0.8V Industrial Designs
- Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?
- The Facts: Why Accelerated VIP Is Needed for SoC Verification
- Hand-crafted for horsepower: Apple A6 SoC
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car