What’s on the Horizon for NAND and DRAM?
February 5, 2010
January is a time where lots of planning and forecast are made, with high hopes usually. Semiconductor memory industry, after several years of prolonged downturn, finally started to see some glimpses of recovery lately. Prices are improving, product migrations happening, new process node migration providing production efficiency and hopefully more profitability to the manufacturers.
Related Semiconductor IP
- DFI 6.0 Verification IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
Related Blogs
- More signs of spring for the 2010 DRAM market
- DRAM vendors look to 40nm process technology to keep DRAM profits flowing next year
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
- AMD GPUs using new HBM DRAM (and the cost/benefit appears balanced!)