Is Design in India on the Upswing?
The India Electronics and Semiconductor Association (IESA) recently organized a two-day conference on Strategic Electronics, and, not surprisingly, the overriding message was that India needs indigenous chip design and wafer fabrication facilities for its development of Defense and Space electronics.
While the debate on whether or not India needs a wafer fab continues on and off, there is no denying that indigenous chip design is on the upswing – and not just in the Defense sector. This is not to be confused with the cutting-edge work happening at captive design centers of multi-national corporations; we are talking about Indian companies designing and launching chips that are 100% designed in India.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- The Missing Layer in AI Systems Design is Predictable, Scalable Data Movement
- Analog Design and Layout Migration automation in the AI era
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- Verification Sanity in Chiplets & Edge AI: Avoid the “Second Design” Trap
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing