Instruction Decoders: RISC vs CISC
December 17, 2020
In my post The Start of the Arm Era I said that it feels like something significant is changing. There's something Arm-y in the air. Suddenly Arm is faster than all x86 processors except the highest end of AMD's line. But why now? The three big announcements have been:
- Amazon AWS's Graviton 2 (from its Annapurna subsidiary)
- Arm's own Cortex-X1 (see my post Arm Goes for It)
- Apple's M1 (also covered in Arm Goes for It)
I think that there are two reasons for this flurry of activity. One business. One technical.
To read the full article, click here
Related Semiconductor IP
- nQrux Secure Boot
- 4K/8K Multiformat IP supporting AV2 decoder
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
Related Blogs
- A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Effectively hiding sensitive data with RISC-V Zk and custom instructions
- The Semiconductor World vs TSMC vs EDA
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA