Instruction Decoders: RISC vs CISC
In my post The Start of the Arm Era I said that it feels like something significant is changing. There's something Arm-y in the air. Suddenly Arm is faster than all x86 processors except the highest end of AMD's line. But why now? The three big announcements have been:
- Amazon AWS's Graviton 2 (from its Annapurna subsidiary)
- Arm's own Cortex-X1 (see my post Arm Goes for It)
- Apple's M1 (also covered in Arm Goes for It)
I think that there are two reasons for this flurry of activity. One business. One technical.
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