How Will EDA Benefit from the AI Revolution?
With the rise in demands for instant gratification, high performance, and smart everything, we are witnessing how AI inclusion in almost every industry revolutionizes productivity, design, and performance. The EDA (Electronic Design Automation) industry is no different; using AI (artificial intelligence) across the EDA design suite is the solution to improve performance and productivity. During the recent CadenceLIVE’23 Europe, I got a chance to witness a panel discussion with an exciting title: How Will EDA Benefit from the AI Revolution?
The panel was moderated by Rosa Markarian and composed of renowned experts from industry and academia, as mentioned below:
- Rod Metcalfe from Cadence
- Jean-Christophe Glas from Arm
- Hussam Amrouch from TU Munich
- Hammond Pearce from the University of New South Wales in Sydney (UNSW Sydney)
In the hour-long session, the experts delved into the various aspects of applying generative AI in EDA in front of a packed audience. The moderator, Rosa Markarian, confidently stated that EDA is one of the few industries that doesn't see Generative AI as a job killer but rather as a welcoming solution to boost the productivity of engineers and combat the widening engineer gap. Nevertheless, many issues must be resolved, including copyright issues of the created code or hallucination of GPT systems. Apart from this, there were many intriguing discussion topics, such as
- AI, its impact on jobs, and is AI a job killer in the EDA industry?
- How AI is helping to bridge the gap and meet the shortage of skills in the semiconductor industry
- Where are we on Gartner’s research cycle?
- Challenges in verification and increasing cost
- The impact on academia
and many more that I am going to reveal in this blog series. The panel discussion started with an interesting discussion about the impact of generative AI on chip design.
To read the full article, click here
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- How Will EDA Benefit from the AI Revolution? - Part 2
- What will EDA and chip design look like in the year 2020? Prognostications from the ICCAD panel
- From All-in-One IP to Cervell™: How Semidynamics Reimagined AI Compute with RISC-V
- LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car