How to Achieve Faster Signoff of Billion-Gate, Low-Power SoCs

By Synopsys, Inc.

April 6, 2023

The fact that the battery for your multi-tasking, feature-rich smartphone can run as long as it does between charges is a testament to the delicate power management tradeoffs that mobile device designers must perform. Chips running in today’s phones commonly have billions of gates, upwards of 20 million lines of code, and hundreds of power domains. Keeping the device at optimal, energy-efficient performance levels requires the right balance.

For years now, chip designers have designed their SoCs so that certain parts go into sleep mode when they aren’t needed. For example, if you’re using a mapping application on your smartphone, the part of the chip responsible for running your email system can be shut off. Ensuring that the chip is ready for prime time, however, can be a daunting task.

Considering the size and complexity of today’s low-power SoCs, verification and signoff are growing increasingly challenging. Yet, these steps are more critical than ever, as undetected bugs could prove detrimental or even fatal to the chip. Fortunately, SoC verification technologies have evolved to support today’s massive chip designs. For example, Synopsys VC LP™ static low power verification solution provides more than 650 checks with full-chip capacity and performance for complete low-power static signoff. And now, the solution has been enhanced with advanced functional checks that allow verification engineers to catch potential functional issues that would otherwise be very resource-intensive to detect during simulation. Read on to learn more about how the Synopsys VC LP solution facilitates faster, more comprehensive debug to help you deliver high-quality, high-performing silicon.

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