What You Need to Know About Gate-All-Around Designs

By Synopsys, Inc.

May 2, 2024

For several generations of semiconductor technology, chip designers have derived great benefit from FinFETs, the three-dimensional field-effect transistors (FETs) marked by their thin vertical fins. However, the industry is now running into the limits of how much we can further shrink FinFETs, whilst extracting the speed and power benefits, which are needed for compute-intensive applications like artificial intelligence (AI) and machine learning (ML). Enter the gate-all-around (GAA) transistor architecture, which extends device scaling while increasing chip performance and reducing power.

GAA devices began to emerge at 3nm and are dominant at 2nm. Currently, high-performance mobile is leading the way in GAA adoption, with hyperscale servers and high-performance CPUs following closely behind. SemiEngineering calls the GAA transistor “the ultimate CMOS device in terms of electrostatics.” As the industry marches into the angstrom era and scaling alone becomes increasingly challenging, GAA transistors—alongside new power distribution schemes and multi-die based design—are poised to help accelerate semiconductor innovation.

Read on for more details about how transistors have evolved over the years, why GAA devices are the transistor architecture of choice in the angstrom era, and how co-optimizing foundation IP and design flows can help SoC design teams achieve GAA success.

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