An inconvenient truth about using DDR3 SDRAM for embedded designs

By Cadence

June 7, 2010

DDR (double data rate) memory chips mounted on DIMMs have long been the mainstay of the PC and server industries. The resulting sales volumes often make these DIMMs the best value available today in terms of cost per bit. PC DIMMs have been 64 bits wide through all DDR generations from the original DDR (also called DDR1) parts to today’s DDR3 chips. Many embedded designs also use PC DIMMs because their high sales volumes make them a relatively cheap source of high-capacity DRAM. However, DDR3 memories have one key characteristic that may make 64-bit DDR3 DIMMs a poor choice for many embedded designs: DDR3 SDRAMs use an 8n prefetch architecture (eight bits fetched or stored in parallel from the memory array per DDR3 data pin) to keep pace with ever-escalating RAM capacity and memory transfer rates while keeping memory bit-cell access speeds and cycle times reasonable. As a result, DDR3 SDRAMs only support 8-beat data bursts so DDR3 chips integrated into PC DIMMs with 64-bit word widths will transfer 64 bytes per data burst. While 64-bit DDR3 DIMMs match up well to microprocessors with 64-byte cache-line buffers, they do not work very well with microprocessors that have 32-byte cache-line buffers and many embedded processors still employ such buffers.