Functional verification concepts have to change
March 8, 2012
Last week was DVCon, probably the best conference of the year for those interested in functional verification. DVCon stands for Design and Verification Conference and it used to be that it concentrated on design. That was when languages such as Verilog and VHDL were the hot issues of the day. Today, languages such as SystemVerilog and SystemC are hot and verification methodologies such as VMM, eRM, OVM and UVM are even hotter and emerging faster than most companies can keep up with. Of course, the earlier version were there to hide problems with SystemVerilog implementation, but today it is an attempt to help users get a jump start on the creation of a testbench.
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