Functional Coverage Plan Management - What's the Secret Sauce?
March 3, 2014
Verification completeness of design functionality is a very important aspect for verification engineer. You could say it is almost as important as food is to life!
One very important metric towards verification completeness is functional coverage. Functional coverage is a guide for directing verification completeness and convergence, by identifying covered and uncovered portions of the design. However, defining coverage can be quite a tedious process, especially when dealing with a complex design. So whats our secret sauce to solve this problem? Read on to find out.
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Blogs
- Increasing Verification Productivity Through Automation of Functional Coverage Management
- The Role of Coverage in Formal Verification, Part 1 of 3
- In Verification, Failing to Plan = Planning to Fail
- Is Your Functional Coverage Stuck at 70%?
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions