Functional Coverage Plan Management - What's the Secret Sauce?
March 3, 2014
Verification completeness of design functionality is a very important aspect for verification engineer. You could say it is almost as important as food is to life!
One very important metric towards verification completeness is functional coverage. Functional coverage is a guide for directing verification completeness and convergence, by identifying covered and uncovered portions of the design. However, defining coverage can be quite a tedious process, especially when dealing with a complex design. So whats our secret sauce to solve this problem? Read on to find out.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Increasing Verification Productivity Through Automation of Functional Coverage Management
- Is Your Functional Coverage Stuck at 70%?
- Management of Projects - Is it really working?
- Inventors & IP Management: Bill Meade Interview
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing