The Role of Coverage in Formal Verification, Part 1 of 3
As outlined in a prior post, new advances in formal and multi-engine technology (like Incisive Enterprise Verifier or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less. Given this premise, it's natural to ask: "OK, but how does formal and multi-engine assertion-based verification (ABV) fit into the coverage and metric-driven work flow that I am (A) familiar with, and (B) know is effective in measuring my progress?" In the following series of blog posts, I'll answer these important questions. To spare you some suspense: conceptually, the coverage-driven verification terms and methodologies you are familiar with when writing testbenches and/or constrained-random stimulus in e or SystemVerilog - terms like "constraints'" "code coverage," and "functional coverage" -- have essentially the same meaning in the formal-centric ABV world.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Blogs
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- Reducing Manual Effort and Achieving Better Chip Verification Coverage with AI and Formal Techniques
- How AI Drives Faster Chip Verification Coverage and Debug for First-Time-Right Silicon
- Raising RISC-V processor quality with formal verification
Latest Blogs
- CDM Dependence on Device Capacitance
- What the Cyber Resilience Act means for the future of chip design
- When Your IP Vendor Has Operated 150,000 Base Stations: Introducing Viettel Semiconductor
- Relationship between architecture and validation in system design
- The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era