The Role of Coverage in Formal Verification, Part 1 of 3

By _Cadence - Functional Verification Blog

January 3, 2011

As outlined in a prior post, new advances in formal and multi-engine technology (like Incisive Enterprise Verifier  or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less.  Given this premise, it's natural to ask: "OK, but how does formal and multi-engine assertion-based verification (ABV) fit into the coverage and metric-driven work flow that I am (A) familiar with, and (B) know is effective in measuring my progress?"  In the following series of blog posts, I'll answer these important questions.  To spare you some suspense: conceptually, the coverage-driven verification terms and methodologies you are familiar with when writing testbenches and/or constrained-random stimulus in e or SystemVerilog - terms like "constraints'" "code coverage," and "functional coverage" -- have essentially the same meaning in the formal-centric ABV world.

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