In Verification, Failing to Plan = Planning to Fail

By _Cadence - Functional Verification Blog

January 14, 2011

So I know you tell your kids this, you tell your spouse this, you heard it from your parents and they from theirs, yet somehow when it comes down to it -- it always seems easier to "do" than to "plan."  Even redo seems easier than to actually spend the time to write out a meaningful plan and then execute to it.  So why does the recent Cadence verification news revolve around the verification plan?

Because it is exactly what is needed to be successful with increasingly complex FPGA and ASIC designs! With the advent of and soon massive proliferation of the Universal Verification Methodology (UVM), this concept is even more critical than ever before.  Why? The power of UVM allows you to literally outstrip your ability to use it, as you can generate more information than you can consume if you're not careful. 

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