Reducing Manual Effort and Achieving Better Chip Verification Coverage with AI and Formal Techniques
Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the chip development cycle. Coverage lies at the very heart of this process, providing the best way to assess verification progress and determine where to focus further effort. Code coverage of the register transfer level (RTL) chip design, functional coverage as specified by the verification team, and coverage derived from assertions are combined to yield a single metric for verification thoroughness.
Coverage goals are usually quite high (95% or more) and hard to achieve. Chip verification engineers spend weeks or months trying to hit unreached coverage targets to ensure that the design is thoroughly exercised and bugs are not missed. Traditionally this has involved a lot of manual effort, consuming valuable human resources and delaying project schedules. Fortunately, in recent years several powerful techniques have been developed to automate the coverage process, achieve faster coverage closure, and end up with higher overall coverage.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Blogs
- How to Speed Up Simulation Coverage Closure with Formal Verification Tools
- How AI Drives Faster Chip Verification Coverage and Debug for First-Time-Right Silicon
- Skymizer Reduces Verification Cycles for AI Accelerator IP Development by 33% with Synopsys HAPS Prototyping
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
Latest Blogs
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP
- Why nonce reuse can break AES-GCM security in embedded systems
- PQSecure™-Agility Earns NIST CAVP Validation