EUV Will Not be Ready For 14nm, says Imec President...
EUV will not be ready for 14nm,says the President of Imec, Luc van den Hove.
"I believe the time to decide lithography options for 14nm is basically now, and it's clear EUV is not ready for the challenge," said van den Hove.
One option at 14nm is triple patterning, but this would increase wafer cost by 90% compared to 28nm, said van den Hove.
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