Dynamic Power Estimation Hits Limits of SoC Designs
The unstoppable rise in design sizes has been taxing heavily the EDA verification tools. Dynamic power estimation tools are one example.
Several incentives entice consumers to upgrade their mobile gadgets frequently. From more functionality and enhanced user experience, to a more attractive user interface to enliven usage, lighter weight, longer battery life, and the list does not stop here. All considered, it seems that long battery life tops the list, and longer battery life directly correlates to lower power consumption.
Power consumption in microelectronics has seen a constant drop since the invention of the planar integrated circuit by Noyce and Kilby five decades ago. The planar technology made it possible to scale (shrink) solid-state devices. The smaller the transistors, the more transistors in the same area, the faster they switch, the less energy they consume and the cooler the chips run (for the same number of transistors).
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Blogs
- Securing SoC Reliability with Precision Power-On Reset IP for 0.8V Industrial Designs
- Why Focus Solely on CPU & GPU When Reducing SoC Power?
- FPGA Prototyping of System-on-Chip (SoC) Designs
- Automatically generated analog IP: How it works in SoC designs
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP