Automatically generated analog IP: How it works in SoC designs
In complex system-on-chip (SoC) designs with heterogeneous voltage domains, the shift from custom analog IP to automated digital implementation is enabling designers to save several months while they don’t have to worry about schedule slips caused by manual analog customizations.
The manual design process for analog IP—which hasn’t changed much since the inception of ICs during the 1960s—is often a bottleneck in the chip design stage. Any change in the original IP introduces a potential for errors and additional verification work. Moreover, the integration of analog IP onto a chip design is a time-consuming process. Especially, when analog circuits are susceptible to the on-chip surroundings.
That’s why the highly manual analog design process, which typically takes several months, is now giving way to automated generation of code for analog IP blocks. The automatically-generated analog IP saves integration time and effort.
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