Data-Driven World Gets a Lift with First Two-Party PCIe v6.0 Linkup by Synopsys and Keysight
Our digital world is swimming in data, and the faster the data gets transferred from one point to another, the better performance you’ll see from an array of applications, like the metaverse, with its enriching interactions. Another example is big data analytics that deliver insights on hugely complex dilemmas, such as vaccine discovery, climate change, or financial forecasting.
Making these experiences and discoveries possible is the PCI Express (PCIe) 6.0 specification, which became available last year and doubles the data transfer rate of its predecessor to a blazingly fast 64 GT/s per pin. Faster data transfer means faster computations for applications like high-performance computing (HPC), AI inference engines, and cloud-based software, as well as for solid-state drives (SSDs) used in data centers.
We may not start to see hardware adopting the latest version of the popular I/O bus specification until later this year; however, Synopsys and Keysight have accomplished an important milestone that promises to spur PCIe v6.0 adoption: the industry’s first two-party 64 GT/s linkup. What this signifies is a clean and successful exchange between two ends of a link without any trips to recovery, which are typically caused by aberrations in signal quality. The next step in this journey is to transfer data, such as memory reads and writes, at the PCIe v6.0 data rate of 64GT/s.
To read the full article, click here
Related Semiconductor IP
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
Related Blogs
- World First: Synopsys MACsec IP Receives ISO/PAS 8800 Certification for Automotive and Physical AI Security
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- The Future of PCIe Is Optical: Synopsys and OpenLight Present First PCIe 7.0 Data-Rate-Over-Optics Demo
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car