CDNLive: Routing at 10nm
At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence reported on what it took to pull together a version of Innovus Implementation System and a version of the ARM physical library that would work cleanly at 10nm. They titled their talk Routing at 10nm, Challenging but Achievable With Collaboration. There are a lot of moving parts in a design like this, with EDA tools from Cadence, standard cells from ARM, the foundry. That is before adding in other IP, and let's not forget about the system/SoC company actually doing the design.
So what's new at 10nm? There is, of course, the usual fact that designs get larger, which stresses the tools more, especially since computers don't keep getting significantly faster every couple of years to bail us out. So what are the other changes at 10nm?
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