Want 10nm Wafers? That'll Cost You
February 11, 2013
As you know, I've been a bit of a bear about what is happening to wafer costs at 20nm and below. At the Common Platform Technology Forum last week there were a number of people talking about this in presentations and at Harvey Jones's "fireside chat".
At the press lunch I asked about this. There are obviously lots of technical issues to address to get to 10nm and below, and I don't want to underestimate them, but at some point an important question is "at what cost." Historically, with each process generation we have had something like a 50% reduction due to scaling along with a 15% increase in wafer fabrication cost resulting in an overall 35% reduction in cost per transistor.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- No More Cheap Wafers, says Future Horizons
- How Much Cost Reduction Will 450mm Wafers Provide
- Why do we need 450mm wafers?
- Moore's Law good for 14nm, and probably, 10nm: Dr. Wally Rhines
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing