Want 10nm Wafers? That'll Cost You
As you know, I've been a bit of a bear about what is happening to wafer costs at 20nm and below. At the Common Platform Technology Forum last week there were a number of people talking about this in presentations and at Harvey Jones's "fireside chat".
At the press lunch I asked about this. There are obviously lots of technical issues to address to get to 10nm and below, and I don't want to underestimate them, but at some point an important question is "at what cost." Historically, with each process generation we have had something like a 50% reduction due to scaling along with a 15% increase in wafer fabrication cost resulting in an overall 35% reduction in cost per transistor.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Blogs
- No More Cheap Wafers, says Future Horizons
- How Much Cost Reduction Will 450mm Wafers Provide
- Why do we need 450mm wafers?
- Moore's Law good for 14nm, and probably, 10nm: Dr. Wally Rhines
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP