ARM Models: Carbon Inside
ARM used to build their own models. By hand. They had an instruction-set simulator (ISS) called ARMulator that was largely intended for software development, and cycle-accurate models that were intended to run within digital simulators for development of the hardware of ARM-based systems.
There were two problems with this approach. Firstly, ARMulator was built using interpretive technology and consumed approximately 1000 host instructions to simulate each ARM instruction so ran at a few MIPS. Modern virtual platform models use Just-In-Time (JIT) compilation, cross-compiling the ARM code into host instructions and so avoiding any interpreter overhead (the compiler creates overhead but that is minimal for instruction sequences executed many times). They thus run hundreds of times faster, fast enough to boot operating systems and debug industrial-sized loads of embedded software.
To read the full article, click here
Related Semiconductor IP
- Adaptive Voltage Scaling (AVS) Bus Target IP
- Adaptive Voltage Scaling (AVS) Bus Host Controller
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Related Blogs
- Reviewing different Neural Network Models for Multi-Agent games on Arm using Unity
- Small Language Models: Efficient Arm Computing Enables a Custom AI Future
- Cowan LRA model's 2010 semicon sales growth forecast estimate: How does it "stack up" against other prognosticators?
- Jeff Bier's Impulse Response - The Rise of Licensable Cores
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects