Are Standard Cell Libs, Memories and Mixed-signal IP Available at 7nm FF?
More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for clock ranging between 100 MHz to 300 MHz.
That means that Moore’s law has been extremely effective during the last ten years, and also that for a high proportion of designs, speed improvement is a real need. These designs are the natural candidates to target FinFET technologies. From the graph below, you see that moving from 28nm (bulk) to 14nm FF can provide 45% faster frequency, at constant dynamic & leakage power, each step below, 10nm and 7nm, providing another 20% improvement.
To read the full article, click here
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related Blogs
- How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes
- 70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC
- Who Needs to Lead at the 14, 10 and 7nm nodes
- Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24
Latest Blogs
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC
- Secure Boot for embedded systems: Building a complete chain of trust