70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC
The title for this blog entry comes from a statement made early in a presentation on SoC design given at this week’s International SoC Conference in Newport Beach, California. The speaker was Cormac O’Sullivan from the S3 Group in Cork, Ireland. O’Sullivan is the RF and Mixed Signal Engineering Team Lead and S3 is a design house specializing in RF and mixed-signal SoC design. The official title of his presentation was “RF SoC Design Flow.”
Why worry about RF and mixed-signal SoC design?
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Blogs
- Six Issues that will Inhibit Profitable Growth in 2010 - Be Ready
- Real Number Model Development and Application in Mixed-Signal SoC Verification
- IP Roundtable, Part 6: Integration Issues Ahead
- Sneak Peek! Interesting Issues Caught by Our USB 3.0 Validator
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space