51st DAC - in pictures!
July 2, 2014
Its almost a month since DAC happened… and we finally got around to putting up some of the pictures we took during DAC. It was our first time at DAC, and we showcased our JEDEC UFS and MIPI verification IPs. Sharing some moments captured during the short lunch (or should I say sandwitch) breaks!
Related Semiconductor IP
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
Related Blogs
- Why DACs are so crucial in modern chip design
- Verification Sanity in Chiplets & Edge AI: Avoid the “Second Design” Trap
- Ensuring reliability in Advanced IC design
- AI in Design Verification: Where It Works and Where It Doesn’t
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects