Moore’s Law and 40nm Yield
November 29, 2009
To follow up one of my most popular blogs TSMC 40nm Yield Explained!, here is a closer look at the 40nm yield issues that currently plague the semiconductor industry. It’s a direct result of Moore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level.
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related Blogs
- Moore's Law and 28nm Yield
- Blogging from Taiwan: TSMC and 40nm Yield
- TSMC 40nm Yield Explained!
- Moore's (Empirical Observation) Law!
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