10nm SRAM Projections - Who will lead
March 28, 2016
At ISSCC this year Samsung published a paper entitled "A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance, and Area Optimization. In the paper Samsung disclosed a high density 6T SRAM cell size of 0.040µm2. I thought it would be interesting to take a look at how this cell size stacks up to 6T SRAM cells we have seen to-date and some projections for what other companies 10nm 6T SRAM cell sizes might be.
To read the full article, click here
Related Semiconductor IP
- SRAM Memory Model
- QDR II SRAM Controller Intel® FPGA IP Function
- QDR II SRAM Controller Intel® FPGA IP
- ZBT SRAM memory controller
- SRAM Test Solution
Related Blogs
- How much SRAM proportion could be integrated in SoC at 20 nm and below?
- Want 10nm Wafers? That'll Cost You
- Moore's Law good for 14nm, and probably, 10nm: Dr. Wally Rhines
- Traditional Cost Reduction Returns At 10nm, says Globalfoundries
Latest Blogs
- From Bug Hunting to Engineering Methodology: Lessons from AI-Driven Development
- Manufacturing Intelligence: Turning EDA Data into Trusted Action
- Execute-in-Place: Getting More from Embedded NVM
- Rethinking RTL flows with AI-driven hybrid formal verification
- Arm and NVIDIA: Building the trusted compute foundation for the agentic AI era