10nm SRAM Projections - Who will lead
At ISSCC this year Samsung published a paper entitled "A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance, and Area Optimization. In the paper Samsung disclosed a high density 6T SRAM cell size of 0.040µm2. I thought it would be interesting to take a look at how this cell size stacks up to 6T SRAM cells we have seen to-date and some projections for what other companies 10nm 6T SRAM cell sizes might be.
To read the full article, click here
Related Semiconductor IP
- Single Port High-Speed Multi Bank SRAM Memory Compiler on GF 22FDX+
- Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+
- Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+
- SRAM Test Solution
- SRAM Test and Repair Solution
Related Blogs
- How much SRAM proportion could be integrated in SoC at 20 nm and below?
- Want 10nm Wafers? That'll Cost You
- Moore's Law good for 14nm, and probably, 10nm: Dr. Wally Rhines
- Traditional Cost Reduction Returns At 10nm, says Globalfoundries
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA