Traditional Cost Reduction Returns At 10nm, says Globalfoundries
Although there will not be the normal Moore’s Law 30% transistor cost reduction at 20nm, Globalfoundries reckons the successor node – 10nm – will see a return to the traditional cost curve
“The cost is going up but there are technology optimisations that can be implemented, ”
Subi Kengeri vice president for advanced technology architecture, told the Globalfoundries EMEA Technical Seminar in London on Monday.
At the 20nm node, Globalfoundries gets a 2x raw gate improvement and a 16% logic density benefit over 28nm giving cost savings of 7.5 to 8.5% over 28nm.
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