Traditional Cost Reduction Returns At 10nm, says Globalfoundries
October 10, 2013
Although there will not be the normal Moore’s Law 30% transistor cost reduction at 20nm, Globalfoundries reckons the successor node – 10nm – will see a return to the traditional cost curve
“The cost is going up but there are technology optimisations that can be implemented, ”
Subi Kengeri vice president for advanced technology architecture, told the Globalfoundries EMEA Technical Seminar in London on Monday.
At the 20nm node, Globalfoundries gets a 2x raw gate improvement and a 16% logic density benefit over 28nm giving cost savings of 7.5 to 8.5% over 28nm.
To read the full article, click here
Related Semiconductor IP
- 5 GHz 150 fs Jitter PLL - GlobalFoundries 22nm
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- 5 GHz 250 fs Jitter PLL - GlobalFoundries 22nm
- 12-bit, 9.2 GSPS Pipeline ADC - GlobalFoundries 22nm
- Low Power All Digital Fractional-N PLL in GlobalFoundries 12LPP/14LPP
Related Blogs
- Is the Cost Reduction Associated with Scaling Over?
- How Much Cost Reduction Will 450mm Wafers Provide
- Want 10nm Wafers? That'll Cost You
- UMC versus GLOBALFOUNDRIES
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions