This is a 3V to 5V regulated charge pump that will provide up to 100mA output current.
- SMIC
- 180nm
- G
This is a 3V to 5V regulated charge pump that will provide up to 100mA output current.
The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific…
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
LTTS USB 2.0 OTG controller are designed for compliance with USB2.0 specification Revision 2.0 and all associated ECN’s and USB O…
USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
Our company offers a configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications.
The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …
The Synopsys USB 2.0 Controllers support Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) operation based on U…
USB 2.0 On-The-Go IP Core, Compliance Certified
A ‘Dual-Role’ USB 2.0 On-The-Go IP Core that operates as both an USB 2.0 peripheral or as an USB 2.0 OTG host in a point-to-point…
USB 2.0 OTG PHY IP, UMC 55nm SP process
OTG USB 2.0 PHY (VDT and ID are included in PHY), UMC 55nm SP Low-K Logic process.
USB 2.0 OTG PHY IP, OTG, UMC 0.153um Logic process
USB OTG 2.0 PHY, UMC 0.153um Logic process.
USB 1.1 PHY IP, UMC 65nm SP process
ID Detector for USB OTG Function, UMC 65nm SP/HVT Low-K Logic process.
The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev.
USB3.x OTG interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specifica…
USB2.x OTG interface provides full support for the USB2.x synchronous serial interface, compatible with USB 2.0 specification.