USB3.x OTG IIP

USB3.x OTG interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB3.x compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x OTG IIP is proven in FPGA environment. The host interface of the USB3.x OTG can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

USB3.x OTG IIP is supported natively in Verilog and VHDL

• USB 3.0/3.1/3.2 Common support
• Compliant with USB 3.0/3.1/3.2 specification
• Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2
• Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
• Configurable PIPE Interface width 8, 16 or 32 bits
• Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)
• Supports Interrupt/Bulk/Isochronous/Control Transfers
• Control transfers supported by Endpoint 0
• Separate Endpoint Buffers for IN bound and OUT bound packets
• Supports lane polarity inversion
• Supports extensible Host Controller Interface(xHCI)
• Supports Scrambler/Descrambler
• Option to enable/disable scrambling
• Supports SS Bulk Streaming Endpoints, and USB 2.0 High Bandwidth Interrupt and Isochronous endpoints.
• Supports configurable endpoint characteristics – for Maximum Packet Size, Endpoint Type etc.
• CRC32 Checking and generation for SS Data and Header Packets.
• CRC16 checking and generation for HS/FS/LS data packets.
• CRC5 generation and checking for Tokens.
• Supports Split Transfers for FS/LS devices connected to HS Hubs while operating in Embedded Host Mode.
• Supports preamble for LS transfers while operating in Embedded Host Mode.
• Supports Protocol Layer Error Handling.
• Provides prioritized scheduling for periodic endpoints.
• Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
• Supports USB Suspend state and supports remote wakeup devices.
• Supports all HS/FS USB Link Power Management States – L1, L2.
• Supports all SS USB Link Power Management States – U1, U2, and U3.
• Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.
• Support for clock gating and multi-power-well support.
• Supports USB 3.0 Link Power Management
• Support USB 2.0 LPM transactions.
• Supports USB 3.0 Loopack and Compliance Mode.
• Support USB 2.0 Test mode.
• Configurable number of Downstream ports for Embedded Host Applications.
• Supports multiple devices connected under SS/HS/FS hub for Embedded Host Applications
• USB 3.0
• Supports Gen1 super speed with 5GT/s data rate
• Supports single lane
• Supports ADP,HNP,SRP and RSP
• Supports LCRD_A to LCRD_D Credits
• USB 3.0 OTG
• Supported devices
• SS-OTG
• SSPC-OTG Devices
• SS-PO Devices
• SS-EH Devices
• Supported protocols
• SRP
• HNP
• ADP
• RSP for USB 3.0
• Supported speeds
• SS,HS and FS
• Supported feature selector
• b_hnp_enable
• a_hnp_support
• a_alt_hnp_support
• NTF_HOST_REL
• B3_RSP_ENABLE
• Support the all timeout condition
• a_wait_vfall_timout
• a_wait_vrise_timout
• a3_polling_tmout
• a3_recovery_tmout
• a3_rx_detect_active_tmout
• rsp_cnf_err_tmout
• rsp_ack_err_tmout
• rsp_wrst_err_timout
• b3_polling_tmout
• b3_recovery_tmout
• b3_rx_detect_active_tmout
• Combination of SSPC-OTG device communication
• SSPC-OTG device to SSPC-OTG device
• SSPC-OTG device to SS-OTG device
• SS-OTG device to SSPC-OTG device
• USB 3.1
• In addition to USB3.0 features,USB3.1 supports the following features
• Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)
• Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed
• Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports
• Supports SuperSpeedPlus Precision Time Measurement
• Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet
• Supports Length field replica
• Supports Endpoint companion descriptor
• Supports Type-A and Type-B credits
• Supports 128B/132B Encoding/Decoding
• USB 3.2
• In addition to USB 3.0 and USB 3.1 features, USB 3.2 supports the following features.
• Supports Dual lane
• Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed
• Supports Deskew buffer
• Supports Data striping in dual lanes
• Supports Configuration summary descriptor
• Supports link error count and soft error count
• Supports retimer connectivity models
• Supports all the Retimer state machine states[RTSM]
• Supports SRIS and Bit-Level Retimers functionality
• Supports Retimer presence announcement through LBPM
• Support DMA (Optional)
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The USB3.x OTG interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.