RapidIO IP Listing

RapidIO Verification IP provides an smart way to verify the RapidIO bi-directional two-wire bus.

• RapidIO

RapidIO Synthesizable Transactor provides a smart way to verify the RapidIO bi-directional two-wire bus.

• RapidIO

RapidIO EP interface provides full support for the RapidIO EP synchronous serial interface, compatible with RapidIO Interconnect …

• RapidIO

Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II Intel offers two distinct Intel® FPGA IPs for …

• RapidIO

Serial RapidIO is a communication protocol developed to ensure fast and reliable interconnection between the vendor's boards.

• RapidIO

The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.

• RapidIO
• Fully compliant with the Ra…

The RapidIO Verification IP (VIP) provides capable compliance verification solution for the RapidIO protocol.

• RapidIO

The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, hig…

• RapidIO

The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2.

• RapidIO

The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a flexible and o…

• RapidIO

LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support For the Serial RapidIO Gen 2 Xi…

• RapidIO

The RapidlO-AXI Bridge (RIO-AXI Bridge) is a flexible and configurable IP used along with the native RapidlO Controller (GRIO) to…

• Protocol Bridge
• Gold
• Now

The RapidlO Controller solution (GRIO™) is a flexible and configurable IP.

• RapidIO
• Gold
• Now
• RapidIO specification, Revi…

Extoll’s SerDes architecture is based on digital design elements and methodologies.

• GlobalFoundries
• 12nm
• LP

Extoll’s SerDes architecture is based on digital design elements and methodologies.

• GlobalFoundries
• 12nm
• LP

Extoll’s SerDes architecture is based on digital design elements and methodologies.

• GlobalFoundries
• 22nm
• FDX

0.6G - 12.5G Universal SerDes

• Multi-Protocol PHY

The LogiCORE™ IP UltraScale™ FPGAs Transceivers Wizard generates customized HDL to configure the UltraScale FPGA on-chip serial t…

• Multi-Protocol PHY

The LogiCORE™ Virtex®-6 GTXTransceiver Wizard automates the task of creating HDL wrappers to configure the on-chip GTX transceive…

• Multi-Protocol PHY

The LogiCORE™ IP Virtex-5 FPGA RocketIO GTX Transceiver Wizard automates the task of creating HDL wrappers to configure the Xilin…

• Multi-Protocol PHY