RapidIO Controller with V4.1 Support

The RapidlO Controller solution (GRIO™) is a highly flexible and configurable IP. The RapidlO Controller Solution can be used as a Host or device. The RapidlO Controller when used along with the RapidlO to AXI Bridge (RAB) provides high speed multi-channel DMA Data Message and Data streaming functionality to match the bandwidth requirements of the RapidlO interface.

The RapidlO Controller has a simple, configurable and layered architecture, independent of applications, implementation tools, PHY Designs or most importantly target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The RapidlO solution provides highly scalable bandwidth through a configurable data path width and clock frequency.

The solution allows the licensees to easily migrate among FPGA Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. The solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.

Configurable Options

• PIO, DMA, Message, Data streaming or mixed mode of operation
• Parallel/Serial mode of operation
• Bypass support

Design Attributes

• Highly modular and configurable design
• Layered architecture
• Fully synchronous design
• Supports both sync and async reset
• Clearly demarked clock domains
• Software control for key features
• Multiple loop backs for debug

• Compliant to RapidlO Specifications revision 4.0.
• Compliant with RapidlO Error Management Extension specification, Revision 4.0.
• Implements Logical, Transport and Physical layers functions.
• Architected for high link utilization and low latency.
• Efficient receive and transmit buffering scheme.
• Implements receiver controlled flow control.
• Provides Packet oriented user logic interface.

• Serial and Parallel Interfaces supported
• 1x, 2x and 4x serial interface
• 64/128/256-bit internal data path
• PBUS interface for configuration register access
• Up to 256 bytes data payload
• Hardware error recovery
• Exhaustive error reporting and handling
• Pass-Through mode of operation for RIO packets up to 288 bytes
• Accept all Mode of operation for fall over support
• 34/50/66b addressing, 8/16/32b Device ID

• Base Stations
• Storage
• Networking and communications
• General purpose system chip interconnect for any compute platform

• Product Package
  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
•  Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide