Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth,…
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devic…
DisplayPort Intel® FPGA IP Core
Intel now offers a fully VESA-compliant DisplayPort Intel® FPGA IP core v1.4.
DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC 28HPC+, N/S orientation
The DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC 12FFC, N/S orientation
The DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC N7, 1.8V, N/S orientation
The DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC N6, 1.8V, N/S orientation
The DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
Low-power, long-reach, multi-protocol PHY for PCIe 4.0 The Cadence® 10Gbps multi-protocol PHY IP provides a flexible PHY IP that …
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
SerDes requirements for system-on-chip (SoC) designs are becoming increasingly demanding and must support increasing numbers of p…
Proven PHY IP for USB3.1 with supporting multi-protocol feature The ® IP for 10Gbps Multi-Protocol PHY simplifies the design proc…
The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and aut…
Verification IP for DisplayPort/eDP/DSC/DPI
A comprehensive VIP solution for DisplayPort (DP) and eDP source and sink designs.
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 55SP
The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP
The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in UMC 40SP
The Display Port 1.4 Rx IP Channel's maximum capacity is supported.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 40SP
Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 28HPC
The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).