DRAM IP Listing

Low Latency DRAM Memory Model provides an smart way to verify the Low Latency DRAM component of a SOC or a ASIC.

• DDR

Low Latency DRAM Synthesizable Transactor provides a smart way to verify the Low Latency DRAM component of a SOC or a ASIC in Emu…

• DDR

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

• UMC
• 90nm
• SP
• Pre-Silicon

IP

• SMIC
• 65nm
• LL
• Silicon Proven

IP

• SMIC
• 55nm
• LL
• Silicon Proven

IP

• SMIC
• 65nm
• LL
• In Production

IP

• SMIC
• 65nm
• LL
• In Production

IP

• SMIC
• 55nm
• LL
• In Production

NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being reliable and secure.

• eFuse / OTP
• In Production

NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being reliable and secure.

• eFuse / OTP
• In Production

This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products.

• TSMC
• 7nm
• N7+

This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products.

• TSMC
• 7nm
• N7+
• Available on request

This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products.

• TSMC
• 7nm
• N7+
• Available on request

This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products.

• TSMC
• 7nm
• N7+
• Available on request

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• Samsung
• 5nm
• SF5

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• LPDDR
• Silicon Proven
• Now
• JEDEC, JESD209-5A, JESD209-…

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as …

• GDDR
• Silicon Proven
• Now
• JEDEC, JESD250, GDDR6

This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput.

• TSMC
• 28nm
• HPC+
• In Production

Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduli…

• DDR

The OL_H264E-CFS core is a hardware implementation of the H.264 video compression algorithm.

• Video Processing
• Proven in ASIC and FPGA
• Now
• ITU-T H.264 specification