Vendor: SmartDV Technologies Category: DDR

Low Latency DRAM Memory Model

Low Latency DRAM Memory Model provides an smart way to verify the Low Latency DRAM component of a SOC or a ASIC.

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Overview

Low Latency DRAM Memory Model provides an smart way to verify the Low Latency DRAM component of a SOC or a ASIC. The SmartDV's Low Latency DRAM memory model is fully compliant with standard Low Latency DRAM Specification and provides the following features. Better than Denali Memory Models.

Low Latency DRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Low Latency DRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports Low Latency DRAM memory devices from all leading vendors.
  • Supports 100% of Low Latency DRAM protocol standard Low Latency DRAM specification.
  • Supports programmable clock frequency of operation.
  • Supports 8 internal banks.
  • Supports for all Mode registers programming.
  • Supports Programmable Read latency and Row cycle time.
  • Supports Address Multiplexing.
  • Supports all the Low Latency DRAM commands as per the specs.
  • Supports for Programmable burst lengths.
  • Supports Data Mask for Write commands
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Support for Power Down features.
  • Support for Self Refresh features.
  • Supports for DLL.
  • Supports for ODT (On-Die Termination).
  • Support all types of timing and protocol violation detection.
  • Constantly monitors Low Latency DRAM behavior during simulation.
  • Protocol checker fully compliant with Low Latency DRAM Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

Low Latency DRAM Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of Low Latency DRAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the Low Latency DRAM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
Low Latency DRAM Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is Low Latency DRAM Memory Model?

Low Latency DRAM Memory Model is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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