Vendor: SmartDV Technologies Category: DDR

Low Latency DRAM Synthesizable Transactor

Low Latency DRAM Synthesizable Transactor provides a smart way to verify the Low Latency DRAM component of a SOC or a ASIC in Emu…

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Overview

Low Latency DRAM Synthesizable Transactor provides a smart way to verify the Low Latency DRAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's Low Latency DRAM Synthesizable Transactor is fully compliant with standard Low Latency DRAM Specification and provides the following features.

Key features

  • Supports 100% of Low Latency DRAM protocol standard Low Latency DRAM specifications
  • Supports 8 internal banks
  • Supports all mode registers programming
  • Supports programmable read latency and row cycle time
  • Supports address multiplexing
  • Supports all the Low Latency DRAM commands as per the specs
  • Supports programmable burst lengths
  • Supports data mask for write commands
  • Checks for following:
    • Check-points include power on, initialization and power off rules
    • State based rules, active command rules
    • Read/Write command rules etc
    • All timing violations
  • Supports power down features
  • Supports self refresh features
  • Supports DLL
  • Supports ODT (on-die termination)
  • Supports all types of timing and protocol violation detection
  • Protocol checker fully compliant with Low Latency DRAM specification
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

Low Latency DRAM Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the Low Latency DRAM testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
Low Latency DRAM Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is Low Latency DRAM Synthesizable Transactor?

Low Latency DRAM Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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