Memory Controller

Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduling algorithm and high-speed implementation. Designed to address the needs of next-generation SoCs, the OMC saves a significant amount of area and power while supporting the highest levels of the DRAM bandwidth.

OMC integrates seamlessly with the OPENEDGES DDR PHY(OPHY) and On-Chip Interconnect (OIC) to deliver a complete memory subsystem. OMC also supports third-party DDR PHYs, providing full functional verification for use with any PHY implementation. 

DDR Memory Type

OMC Configurable Options

• DRAM types (LPDDR6/5x/5/4x/4, DDR5/4x/4/3, GDDR6, HBM3)
• Channel DQ width (x4, x8, x16, x32, x64)
• Number of AXI master ports (up to 5)
• AXI master data width and frequency
• Customizable Request queue depth
• Configurable write and read data queue depth
• Active QoS with OPENEDGES On-chip Interconnect IP
• AES-Based integrated memory encryptor

DRAM Support 

• JEDEC compliant LPDDR6/5x/5/4x/4/3, DDR4/3, GDDR6, HBM

High Performance 

• A proprietary out-of-order scheduling algorithm​
• Dual-PHY control for 2x DRAM channel bandwidth with a single OMC instance

Low Power Consumption

• Ultra-low power consumption with HW-controlled dynamic DRAM frequency scaling
• Automatically handles training activities required for frequency change
• Automated DRAM power management​

​​Special Features

• BFE (Bus Front End) for multi-master ports (optional)

Workload-Driven Performance Optimization​

• Intuitive visualization and analysis of memory subsystem architecture and performance
• Workload-driven memory subsystem architecture and QoS optimization

Intensive DRAM Utilization

• Over 90% DRAM utilization using a proprietary out-of-order scheduling algorithm
• Optimal pipeline architecture

​Ultra-Low Power Consumption

• Hardware-controlled dynamic DRAM frequency scaling
• Automates training activities required for frequent changes​
• Highly area-efficient​

​Extremely Low Latency

• Low latency even in high utilization scenarios
• Suppression of peak latency using the latency-aware algorithms

​Safety & Security

• Inline ECC AN link ECC
• Features link error detection, security firewall
• Retry on data link error
• Achieved ISO 26262

OMC is packaged with the following items for all eligible companies:

• IP core RTL
• Standalone Simulation Environment
• Management SW
• IP Documentation