What is SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application?
SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application is a LPDDR IP core from SMIC listed on Semi IP Hub. It is listed with support for smic Silicon Proven.
Vendor:
SMIC
Category:
LPDDR
SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
Key features
- DDR3/DDR2/LPDDR2 COMBO interface for DRAM application;
- SMIC 65nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) 40um * 270um with DUP stagger bonding pads;
- Work IO voltage: 1.2V/1.5V/1.8V;
- Programmable driven-strength, programmable ODT,support DDR3-1333,DDR2-1066,LPDDR2-1066;
- Suitable for 7, 8, 9 and 10 layers application ;
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 65nm | LL | Silicon Proven |
Specifications
Identity
Part Number
SP65NLLD2P_MEMIO_COMBO3
Vendor
SMIC
Type
Silicon IP
Controller / PHY
Controller
Provider
HQ:
China
Frequently asked questions about LPDDR Interface IP
How should engineers evaluate this LPDDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.