MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
Consumer Multimedia Applications: Wide support of Consumer PHY standards such as PCIe Gen1/2/3, USB 3.0 Super Speed, JESD204B, SA…
Complete 1.6T Ultra Ethernet IP Solution
The 1.6T Ultra Ethernet IP solution, consisting of 1.6T MAC and PCS multi-rate Ultra Ethernet controllers, silicon proven 224G an…
XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces.
112G-XSR Pam4 for TSMC 7nm FinFET CMOS
Accelerating multi-die, multi-chip SoC designs The Cadence® 112Gbps Extra Short Reach (XSR) SerDes IP for TSMC 7nm consists of ei…
The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
112G-ELR PAM4 SerDes PHY - TSMC 5nm
112G-ELR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channels…
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU,…
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
This receiver converts 10 LVDS, (low voltage differential signaling) data streams, into 30bits dual pixel CMOS data plus 10 contr…
V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow …
This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…
This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…
MIPI M-PHY v4.1 IP, Silicon Proven in UMC 28 HPC
The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-…
MIPI M-PHY v3.1 IP, Silicon Proven in UMC 40LP
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3.0 Specification, UniPro v1.8 Specific…
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC
The MIPI M-PHY Gear 4 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4…
Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a pa…
112G Ethernet PHY in TSMC (N7, N5, N3P)
The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth…