RapidIO Verification IP provides an smart way to verify the RapidIO bi-directional two-wire bus.
- RapidIO
RapidIO Verification IP provides an smart way to verify the RapidIO bi-directional two-wire bus.
RapidIO Synthesizable Transactor
RapidIO Synthesizable Transactor provides a smart way to verify the RapidIO bi-directional two-wire bus.
RAPIDIO EndPoint Controller IIP
RapidIO EP interface provides full support for the RapidIO EP synchronous serial interface, compatible with RapidIO Interconnect …
Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II Intel offers two distinct Intel® FPGA IPs for …
Serial RapidIO is a communication protocol developed to ensure fast and reliable interconnection between the vendor's boards.
The so_ip_srio_ctrl is a soft core implementation of Serial RapidIO controller as defined in the RapidIO specification 2.2.
The RapidIO Verification IP (VIP) provides capable compliance verification solution for the RapidIO protocol.
Serial RapidIO 2.1 Endpoint IP Core
The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, hig…
Serial RapidIO - Physical Layer Interface
The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2.
LogiCORE IP Serial RapidIO Gen 2
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a flexible and o…
LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support For the Serial RapidIO Gen 2 Xi…
The RapidlO-AXI Bridge (RIO-AXI Bridge) is a flexible and configurable IP used along with the native RapidlO Controller (GRIO) to…
RapidIO Controller with V4.1 Support
The RapidlO Controller solution (GRIO™) is a flexible and configurable IP.
32G Multi Rate Very Short Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
Extoll’s SerDes architecture is based on digital design elements and methodologies.
32G Multi Rate Long Reach SerDes PHY - GlobalFoundries 12LP and 12LPP
Extoll’s SerDes architecture is based on digital design elements and methodologies.
32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
Extoll’s SerDes architecture is based on digital design elements and methodologies.
0.6G - 12.5G Universal SerDes
UltraScale FPGAs Transceivers Wizard
The LogiCORE™ IP UltraScale™ FPGAs Transceivers Wizard generates customized HDL to configure the UltraScale FPGA on-chip serial t…
Virtex-6 FPGA GTX Transceiver Wizard
The LogiCORE™ Virtex®-6 GTXTransceiver Wizard automates the task of creating HDL wrappers to configure the on-chip GTX transceive…
Virtex-5 FPGA RocketIO GTX Transceiver Wizard
The LogiCORE™ IP Virtex-5 FPGA RocketIO GTX Transceiver Wizard automates the task of creating HDL wrappers to configure the Xilin…