FEC and IP Listing

Accelerated confidence in simulation-based verification of RTL designs with Ethernet networking interfaces Avery TSN Ethernet Ver…

• Ethernet

Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7 Av…

• PCI Express

JESD204 (Serial Interface for Data Convertors) is the serial communication protocol developed used with ADC and DAC.

• JESD204

JESD204C interface provides full support for the JESD204C synchronous serial interface,compatible with JESD204C version specifica…

• JESD204

JESD204C interface provides full support for the JESD204C synchronous serial interface,compatible with JESD204C version specifica…

• JESD204

The DVB-C Demodulator IP core is a silicon-proven IP core and extracted from the production chip, It is a QAM (quadrature amplitu…

• Modulation Demodulation
• In Production
• Ready to license
• ITU-T J.83 Annexes A/B/C, D…

GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs.

• Multi-Protocol PHY

Industry First, Silicon Proven, 116 Gbps per lane IP core, backed by a portfolio of verification tools, PHY interop, and demos Th…

• JESD204
• Mature
• Available
• JEDEC JESD204 Revision D

This RTP Transmitter IP core implements a full Hardware RTP Transmitter.

• Ethernet
• Available
• Ethernet, SMPTE 2022-2-2007…

Xilinx 40G/100G Ethernet LogiCORE based on Sarance Technologies Best-In-Class Intellectual Property Xilinx High-Speed Ethernet Lo…

• Ethernet

The CMS0022 DVB-C/J.83 Cable Demodulator is a 4th generation design that exploits the vendor’s experience of QAM and OFDM systems…

• Modulation Demodulation

The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specifi…

• Channel Coding
• VESA DisplayPort 1.4

The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified …

• Channel Coding
• VESA DisplayPort 1.4

Silicon agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification The UA Link PCS IP…

• UALink

The Universal Media Access Controller (UMAC) ensures efficient data flow, low latency, and optimized power usage.

• Ethernet

The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specifi…

• Channel Coding
• VESA DisplayPort 1.4

This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integra…

• Modulation Demodulation
• Silicon Proven
• Ready to license
• Certified

The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specif…

• HDMI

The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as spe…

• HDMI

The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…

• Channel Coding
• Silicon Proven
• Immediate
• Certified