Real-Time-Clock Analog, Include 32K XOSC, Capaless LDO, POR, VDT - HHGrace 110nm
Real-Time-Clock Analog, Include 32K XOSC, Capaless LDO, POR, VDT - HHGrace 110nm
- LDO Voltage Regulator
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Real-Time-Clock Analog, Include 32K XOSC, Capaless LDO, POR, VDT - HHGrace 110nm
Real-Time-Clock Analog, Include 32K XOSC, Capaless LDO, POR, VDT - HHGrace 110nm
Power On Reset, Detector 3.3V and 1.8V Domain - UNT 180nm
Power On Reset, Detector 3.3V and 1.8V Domain - UNT 180nm
Analog MUX, Switch Resistance is around 100 Ohm - HHGrace 110nm
Analog MUX, Switch Resistance is around 100 Ohm - HHGrace 110nm
RISC-V-based customizable SoC
IP
IP
IP
IP
IP
IP
16-bit 48KSPS stereo Audio ADC
IP
JESD204C IP core for Speedster®7t FPGAs, optimized for high-performance ADC and DAC interfaces while maintaining full backward compatibility with JESD204B.
Silicon Library (SLI) HDMI 2.0 RX IP solution, which consists of PHY analog IP and digital LINK IP, is compliant with HDMI 2.0b standard.
Silicon Library (SLI) HDMI 2.0 TX IP solution, which consists of analog PHY IP and digital LINK IP, is compliant with HDMI 2.0b standard.
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
Compliant to NIST FIPS PUB 197
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP
Since its standardization of ISO/IEC 10918-1 in 1994, JPEG has been continued to be used as a still image storage format.
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP
TMC’s frame rate converter uses an original frame interpolation technology and creates highly accurate interpolation frames with compact circuit resources.