Specialty OSC IO IP, UMC 0.162um G2 process
UMC 0.162um GII Logic process high frequency OSC crystal Pad.
- Analog
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Specialty OSC IO IP, UMC 0.162um G2 process
UMC 0.162um GII Logic process high frequency OSC crystal Pad.
General Purpose IO IP, 5V tolerance, UMC 0.162um G2 process
UMC 0.162um GII Logic process 5V tolerant Generic IO.
General Purpose IO IP, UMC 0.162um G2 process
UMC 0.162um GII Logic process true 3.3V standard IO Cell Library (0.18um shrink process).
PCI-X Controller IP, PCIX 1.0b, Soft IP
PCI-X 1.0b device/host bridge controller.
Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP
10/100 Ethernet MAC with MII or RMII (Reduced MII) interface.
Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP
10/100/1000 Ethernet Controller with AHB bus.
SATA Controller IP, SATA Gen-3 Host, Soft IP
SATA AHCI host controller with PVCI/AHB/AXI interface.
AHB system Peripheral IP, AHB - to - APB Bridge, Soft IP
The IP is APB Bridge between AHB bus and APB bus.
AHB system Peripheral IP, AHB Arbiter, Soft IP
The IP is AHB Controller composed of ar-Biter, dECOder and Mux.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.162um LL process
UMC 0.162um Logic process Standard Core Cell Library.
AHB system Peripheral IP, SRAM controller, Soft IP
Static memory controller with AHB interface.
AHB system Peripheral IP, SDRAM controller, Soft IP
Synchronous DRAM controller with AHB interface.
Secure digital card host controller with APB interface.
Secure digital card host controller with APB interface.
Compact Flash host interface controller with APB interface.
IP
Keyboard/Mouse controller with APB interface.
Interrupt controller with APB interface
IP
APB Fundamental Peripheral IP, IO controller, Soft IP
General purpose input/output controller with APB interface.
AHB system Peripheral IP, IDE Host controller, Soft IP
IDE host controller with AHB interface.
UART/IrDA controller with APB interface
IP
USB 2.0 Device Controller IP, Device controller, Soft IP
USB 2.0 device controller.