Learn more about GPIO IP core
For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.
This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.
Standard foundry GPIOs are where most designs start and for good reason. When the PDK cells fit your requirements there is no reason to look further. The question is what happens when they don’t.
Most practical photonic systems combine a Photonic Integrated Circuit (PIC), which manipulates photons, with an Electronic Integrated Circuit (EIC) that manipulates electrons. Both types of chips require highly specialized design expertise and dedicated manufacturing processes. Both must also ultimately work together seamlessly. And both can take considerable time and engineering effort to develop from scratch. The best approach for such a design task is to start from proven IP on both sides. Alcyon Photonics and Sofics bring complementary expertise to this challenge.
We joined Siemens EDA, through EDA Solutions in June 2026 for a webinar on why a design that looks perfectly correct on schematic can still fail once it’s extracted from layout, and what that means for specialty I/O verification at advanced nodes.
Most chips live an easy life with room temperature, clean power and a steady supply. The chips in this article do not. They sit inside nuclear reactors, ride on satellites and work next to particle beams, where a single stray particle can corrupt data or destroy a device.
