JEDEC Standard No.
- JESD204
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
JEDEC Standard No.
PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platf…
Digital Video Broadcasting - (DVB-ASI) IP Core
Digital Video Broadcasting (DVB) is a suite of open standards for digital television.
The SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) …
Common Public Radio Interface - IP Core
This document provides technical information about the Lattice Common Public Radio Interface (CPRI) IP core.
XAUI 10Gb Ethernet Attachment Unit Interface
10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to…
The 2.5Gb MAC core can support data rates of 1Gbps or 2.5Gbps in LatticeSC/M™ devices.
IBM 65nm LPE 3.3V/1.2V Power On Reset
The present Power-On-Reset circuit generates system reset pulses (RST) when both the 3.3V and 1.2V power suppliers are turned on.
The I65LPEV25_AMP_01 specifies a rail-to-rail voltage reference buffer.
IBM 65nm 10SF Process 24-Bit Stereo Sigma-Delta ADC/DAC
The I65GV25_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifi…
SMIC 65nm LL 3.3V-2.5/1.2V Power Regulator
This IP is a Low-Dropout (LDO) 3.3V to 2.5V and 1.2V power regulator in SMIC 65nm LL 1.2V/2.5V process.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 65nm 2.5/1.2V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
SMIC 65nm LL 12-Bit 8-Input 1M/200k SAR ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
SMIC 0.13µm 5v-3.3v Power Regulator
This IP is a Low-Dropout (LDO) 5V to 3.3V power regulator in SMIC 0.13μm 3.3V/1.2V Logic process.
This IP is a programmable Analog PLL suitable for high speed clock generation.
MPEG-1/2 – Layer I/II Audio Decoder
The MPEG-1/2 – Layer I/II Audio Decoder (CWda75) is an audio IP core for decoding one audio stream in real-time(1).
90 dB of SNR, 24-bit mono audio ADC, stereo audio DAC with capless headphone driver
Its small silicon area but exhaustive and robust features make shCOD90.RC50 the most competitive solution for your mixed-signal S…
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA.