SHA-512, SHA-384, SHA512/256 and SHA-512/224
The SHA-512 module implements the SHA-512, SHA-384, SHA-512/256 and SHA-512/224 hash algorithms specified in FIPS PUB 180-4, the …
- SHA2 (SHA-224) + 3
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SHA-512, SHA-384, SHA512/256 and SHA-512/224
The SHA-512 module implements the SHA-512, SHA-384, SHA-512/256 and SHA-512/224 hash algorithms specified in FIPS PUB 180-4, the …
The SHA-256 module implements both the SHA-256 and SHA-224 hash algorithms specified in FIPS PUB 180-4, the Secure Hash Standard.
The low power embedded SP SRAM is specifically architected and designed with mobile and IoT applications in mind that demands the…
The low power embedded SP SRAM utilizes a different architecture than typical memory compilers and is designed to be used in SoCs…
Bluetooth Low Energy (BLE) RF IP
The VeriSilicon Bluetooth Low Energy (BLE) RF IP is a 2.4GHz ISM band transceiver which is designed for Bluetooth Smart or IEEE 8…
Single Port SRAM compiler - TSMC 40 nm LP - Non volatile Memory optimized for ultra high density and low power - compiler range u…
Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for ultra high density and low power - 3ML- comp…
The AAC-LC Audio Decoder (CWda87) is an audio IP core for decoding up to 6 audio channels in real-time(1).
Foundry sponsored - sROMet compiler - TSMC 55 nm uLP - Non volatile memory optimized for high density and low power - Dual Voltag…
Metal programmable ROM compiler - Memory optimized for low power - compiler range up to 1024 k
Foundry Sponsored - Metal programmable ROM compiler - TSMC 90 nm LPeF - Non volatile memory optimized for low power - compiler ra…
Single Port SRAM compiler - TSMC 110 nm HV_1.5V_5V_32V - Memory optimized for high density and low power - compiler range up to 3…
Foundry sponsored - Dual Port SRAM compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power - Dual Volta…
Foundry sponsored - Dual Port SRAM compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Voltage - c…
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm uLP - Memory optimized for high density and low power - Dual Vol…
Foundry sponsored - Single Port Register File compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power -…
GUNZIP/ZLIB/Inflate Data Decompression
ZipAccel-D is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZ…
GZIP/ZLIB/Deflate Data Compressor
ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZL…
Ultra-Small 8051-Compatible Microcontroller
The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers.
Single Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and Low power - Dual voltage - compiler range up …
Foundry sponsored - Two Port Register File compiler - TSMC 55 nm HV - Memory optimized fore high density and high speed - compile…