Vendor: Dolphin Semiconductor Category: ROM

sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M

Foundry sponsored - sROMet compiler - TSMC 55 nm uLP - Non volatile memory optimized for high density and low power - Dual Voltag…

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Overview

Foundry sponsored - sROMet compiler - TSMC 55 nm uLP - Non volatile memory optimized for high density and low power - Dual Voltage - compiler range up to 1M

Key features

  • REDUCE DIE COST
  • Via 1 programmable ROM
  • Key patent for high density with a single programming layer
  • Gain in density over alternative ROM designs
  • EXTEND BATTERY LIFE
  • Significant gain in dynamic power consumption compared to alternative ROM
  • No leakage in memory plane and minimal leakage in memory periphery
  • MAKE INTEGRATION EASIER
  • Depending on memory capacity. A large number of MUX options can be selected between 8 and 128
  • High flexibility for address range
  • ENABLE RIGHT ON FIRST PASS DESIGN
  • Complete mismatch validation of the memory architecture taking in account local and global dispersion

Specifications

Identity

Part Number
sROMet-TITAN-DV_TSMC_55nm_uLP
Vendor
Dolphin Semiconductor
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Dolphin Semiconductor

Learn more about ROM IP core

An MLC ROM With Inserted Redundancy and Novel Sensing Scheme

An Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 16M bits (actual 32M bits) density is presented. The MLC ROM is designed by a 0.090 μm CMOS logic process. The ROM cell of 0.40μm ×0.50μm with 0.03μm per step of the channel width and channel length increase is determined to obtain 4 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 5 ns. 4 bits per cell can be achieved by inserting more referencing columns of ROM cells to track and to compensate noise from power and ground bouncing.

A Flexible, Field-programmable ROM Replacement

For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field. Antifuse one-time programmable (OTP) provides a flexible, field-programmable alternative to ROM. An antifuse-based bit cell uses controlled, irreversible thin (gate) oxide breakdown to program a bit.

How to design secure SoCs Part IV: Runtime Integrity Protection

In previous articles, we gave an overview about secure SoC architectures (Part I), about the importance of key management (Part II) and secure boot (Part III) - the first line of defense. Part IV of the series focuses on runtime integrity protection, a paramount, ensuring the application remains secure even during active operation.

Frequently asked questions about ROM IP cores

What is sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M?

sROMet compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 1M is a ROM IP core from Dolphin Semiconductor listed on Semi IP Hub.

How should engineers evaluate this ROM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ROM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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